Large-scale production of particular types of semiconductor devices poses problems peculiar to the type of die, electronic circuits, external connectors, and packaging. For example, so-called “flip-chip” dice comprise electronic devices formed on a semiconductor substrate whose integrated circuitry terminates in an array of conductive sites on a die's active surface, which conductive sites are typically referred to as “bond pads.” External conductive structures exemplified by solder “bumps” or “balls” are attached to the bond pads. In use, the flip-chip die is inverted, positioned atop a substrate with contact pads matching the locations of the conductive structures of the die, and the conductive structures bonded to the contact pads of the substrate. Chip scale, flip-chip configured packages are also typically disposed face down over a higher-level substrate with which the chip scale packages are to be connected.
In order to fabricate flip-chip dice in large quantities, several semiconductor dice are simultaneously fabricated on a wafer. The wafer is then scribed or sawn into individual dice, and finishing operations including packaging are conducted on the singulated dice.
It is typically desirable to apply a supportive or protective dielectric material, such as a solder mask, on at least the active surfaces of semiconductor devices or substrates, such as organic packaging substrates, flip-chip type dice, and chip-scale packages, that will be connected to another semiconductor device or to higher-level packaging. Polymers, glass, and other electrically nonconductive materials may be applied to one or both major surfaces of such semiconductor devices. Conventionally, such dielectric materials are applied to a surface of a semiconductor device prior to forming or attaching conductive structures to bond pads or conductive traces exposed through openings in the material. Openings are formed, for example, by etching, in the material to accommodate the subsequent formation or attachment of conductive structures in the openings.
When conventional techniques are employed to form such a protective dielectric material on a surface of a semiconductor device, it is difficult to form openings in the protective dielectric material and form or attach conductive structures, such as solder bumps or balls, in contact with one another within the openings. Thus, during a TCB (thermo-compression bonding) process, voids may occur in the NCF (nonconductive film, which may also be referred to herein and in the art as a wafer level underfill (WLUF)) between an edge of the protective dielectric material defining at least part of an opening and a surface of a conductive structure therein.
The problem arises due to the abrupt edge of openings resulting from conventional techniques used to form openings in solder masks, which result in abrupt, vertical edge walls of the openings, or even a slight undercut of the edge walls. As a result, a void trapping air between a solder bump and the edge wall of the associated opening may be formed. Voids may occur in various locations, such as along an edge of a solder mask, in between interconnects, or between an interconnect and the side of the solder mask.
Such voids may present reliability issues, particularly when a flowable NCF is employed between stacked semiconductor devices, and specifically shorting between adjacent conductive structures. Typically, NCF is laminated onto the wafer prior to dicing the wafer. Therefore the NCF is on the die already during the stacking process. The voids may compromise the ability of the NCF to provide dielectric isolation between laterally adjacent conductive structures. The NCF keeps solder from moving across multiple interconnects. If a void bridges multiple interconnects, solder can fill the void and cause a short. Also, if there is a void next to an interconnect, the solder can move into the void and cause an open interconnect. Thus, underfill layers with air pockets or voids may not completely support or protect the die or the conductive structures secured to the bond pads thereof. The increased use of NCF materials does not cure the voiding problem. Voids may cause shorting between adjacent traces, semiconductor device delamination from the substrate, and solder flowing into the voids, starving solder joint locations of sufficient solder to effect a robust interconnection.
FIG. 13 is a photograph showing a y-axis cross-section of interconnects 10 and NCF material 12. The interconnects (which may be, for example, Cu, Ni, Sn, or Ag) are electroplated to a semiconductor substrate prior to laminating the NCF material 12 onto the wafer. The structure is then subjected to TCB, at which point the voids 14, appearing in the lower right corner of FIG. 13, are formed.
Attempts have been made to eliminate such voids through the use of multiple overlapping solder masks, each mask having a slightly larger opening than the mask below, resulting in a stair-step edge wall around each opening. Such attempts are not entirely successful, and add time, cost, and complexity to the fabrication process.